EM47FM0888SBA
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by
asserting low on /CS, /RAS, /CAS, /WE, high on BA0, low on BA1 and BA2, while controlling the states of
address pins according to the table below.
BA2 BA1 BA0 A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
TDQS
Level
0
01
0
Qoff
0
Rtt
0
Rtt
D.I.C
AL
Rtt
D.I.C
DLL
TDQS enable
Disabled
A11
0
Output Driver
Impedance Control
A5
A1
DLL Enable
Enable
A0
0
RZQ/6
RZQ/7
0
0
1
1
0
1
0
1
Enabled
1
Disable
1
Reserved
Reserved
Qoff
A12
0
Write leveling enable
Disabled
A8
0
Output buffer enabled
Output buffer disabled
1
Enabled
1
MRS Mode
MR0
BA1
BA0
Rtt_Nom
A9
A6
0
A2
0
Additive Latency
0
A4
0
A3
0
0
0
1
1
0
1
0
1
ODT disabled
RZQ/4
0
0
0
0
1
1
1
1
MR1
0
1
CL - 1
0
1
MR2
RZQ/2
1
0
CL - 2
1
0
MR3
RZQ/6
1
1
Reserved
1
1
RZQ/12
RZQ/8
0
0
0
1
Reserved
Reserved
1
0
1
1
Note1. BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
Note2. Qoff: Outputs disabled - DQs, DQSs, /DQSs.
Note3. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in Write
Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
Note4. New RON value is defined as RON48=RZQ/5.
Jul. 2012
33/39
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