EM47FM0888SBA
Note1. All DDR3 SDRAM commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising
edge of the clock. The MSB of BA, RA and CA are device density and configuration dependant.
Note2. /RESET is low enable command which will be used only for asynchronous reset so must be maintained
HIGH during any function.
Note3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an
(Extended) Mode Register.
Note4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating)
logic level”.
Note5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly (OTF) BL will be defined
by MRS.
Note6. The Power Down Mode does not perform any refresh operation.
Note7. The state of ODT does not affect the states described in this table. The ODT function is not available
during Self Refresh.
Note8. Self Refresh Exit is asynchronous.
Note9. VREF(Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. VREFDQ
supply may be turned OFF and VREFDQ may take any value between VSS and VDD during Self
Refresh operation, provided that VREFDQ is valid and stable prior to CKE going back high and that first
Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self
Refresh.
Note10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait
state. The purpose of the No Operation command (NOP) is to prevent the DDR3 SDRAM from
registerng any unwanted commands between operations. A No Operation command will not terminate
a pervious operation that is still executing, such as a burst read or write cycle.
Note11. The Deselect command performs the same function as No Operation command.
Note12. Refer to the CKE Truth Table for more detail with CKE transition.
Jul. 2012
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