EM47EM1688MBB
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, including RTT_WR impedance
and CAS write latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high
on BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA2 BA1 BA0 A14
0
0
0
0
Rtt_WR
0
0
0
CWL
0
0
1
0
MRS Mode
MR0
BA1
0
BA0
0
Rtt_WR
A10
0
A9
Dynamic ODT off
0
1
0
1
CAS write latency (CWL)
≧ 2.5
A6
A4
A3
0
MR1
0
1
RZQ/4
RZQ/2
0
1
1
5(tCK
ns)
≧ 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
MR2
1
0
＞
6 (2.5ns tCK
.875ns)
≧ 1
1
MR3
1
1
Reserved
＞
7 (1.875ns tCK
.5ns)
.25ns)
0
＞
≧ 1
8 (1.5ns tCK
1
Reserved
Reserved
Reserved
Reserved
0
1
0
1
Note1. BA2, A8, A11 ~ A14 are RFU and must be programmed to 0 during MRS.
Note2. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling,
Dynamic ODT is not available.
CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5). CAS Write Latency is the delay, in clock cycles,
between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not
support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS
Write Latency (CWL); WL = AL + CWL.
Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance
signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be
changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT
settings. In Write leveling mode, only RTT_Nom is available.
Oct. 2013
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