EM47EM1688MBB
Mode Register Definition
Mode Register MR0
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls
burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various
applications. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0, BA1 and BA2, while
controlling the states of address pins according to the table below.
Note1. BA2, A13 & A14 are reserved for future use and must be programmed to 0 during MRS.
Note2. WR (write recovery for autoprecharge) min in clock cycles is calculated by dividing tWR (in ns) by tCK (in
ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in
the mode register must be programmed to be equal or larger than WRmin. The programmed WR value
is used with tRP to determine tDAL.
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