EM47EM0888SBA
Burst Type (A3)
R/W
Burst Length
A2
A1
A0
Sequential Addressing, A3=0 Interleave Addressing, A3=1
R
R
R
R
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
V
0
0
1
1
0
0
1
1
V
V
0
0
1
1
0
0
1
1
V
0
1
0
1
0
1
0
1
V
V
0
1
0
1
0
1
0
1
V
0 1 2 3 T T T T
1 2 3 0 T T T T
2 3 0 1 T T T T
3 0 1 2 T T T T
4 5 6 7 T T T T
5 6 7 4 T T T T
6 7 4 5 T T T T
7 4 5 6 T T T T
0 1 2 3 X X X X
4 5 6 7 X X X X
0 1 2 3 4 5 6 7
1 2 3 0 5 6 7 4
2 3 0 1 6 7 4 5
3 0 1 2 7 4 5 6
4 5 6 7 0 1 2 3
5 6 7 4 1 2 3 0
6 7 4 5 2 3 0 1
7 4 5 6 3 0 1 2
0 1 2 3 4 5 6 7
0 1 2 3 T T T T
1 0 3 2 T T T T
2 3 0 1 T T T T
3 2 1 0 T T T T
4 5 6 7 T T T T
5 4 7 6 T T T T
6 7 4 5 T T T T
7 6 5 4 T T T T
0 1 2 3 X X X X
4 5 6 7 X X X X
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7
R
4 (chop)
R
R
R
W
W
R
R
R
R
8
R
R
R
R
W
Note1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock
cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled
in by two clocks. In case of burst length being selected on-the-fly via A12 (/BC), the internal write
operation starts at the same point in time like a burst of 8 write operation. This means that during
on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
Note2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
Note3. T: Output driver for data and strobes are in high impedance.
Note4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
Note5. X: Don’t Care.
Apr. 2012
32/39
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