EM47DM0888SBA
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by
asserting low on /CS, /RAS, /CAS, /WE, high on BA0, low on BA1 and BA2, while controlling the states of
address pins according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10
A9
Rtt
A8
0
A7
A6
Rtt
A5
A4
A3
A2
Rtt
A1
A0
TDQS
Level
0
0 1
0
Qoff
0
D.I.C
AL
D.I.C
DLL
TDQS enable
Disabled
A11
0
Output Driver
Impedance Control
A5
A1
DLL Enable
Enable
A0
0
RZQ/6
RZQ/7
0
0
1
1
0
1
0
1
Enabled
1
Disable
1
RZQ/5
Qoff
A12
0
Write leveling enable
Disabled
A8
Reserved
Output buffer enabled
Output buffer disabled
0
1
1
Enabled
MRS Mode
MR0
BA1
0
BA0
0
Rtt_Nom
ODT disabled
RZQ/4
A9
0
A6
0
A2
0
Additive Latency
0
A4
0
A3
0
MR1
0
1
0
0
1
CL - 1
0
1
MR2
1
0
RZQ/2
0
1
0
CL - 2
1
0
MR3
1
1
RZQ/6
0
1
1
Reserved
1
1
RZQ/12
1
0
0
RZQ/8
1
0
1
Reserved
Reserved
1
1
0
1
1
1
Note1. BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
Note2. Qoff: Outputs disabled - DQs, DQSs, /DQSs.
Note3. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in Write
Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
Note4. New RON value is defined as RON48=RZQ/5.
May. 2011
34/39
www.eorex.com
EOREX [ EOREX CORPORATION ]
