EM47DM0888SBA
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
-125
(DDR3-1600)
-150
(DDR3-1333)
Speed Bin
Symbol
Units Notes
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
Min.
8
Max.
Min.
8
Max.
tCK
Minmum clock cycle, DLL-off mode
-
-
ns
ns
6
tCH, tCL (AVG) Average CK high/low level width
0.47
6
0.53
0.47
6
0.53
-
-
-
-
-
-
ns
Active bank A to active bank B
command period
tRRD
4
4
nCK
ns
tFAW
Four Activate Window
30
30
tIH(base)
DC100
Address and Control input hold time
(VIH/VIL(DC100) levels)
120
45
-
-
-
-
-
-
-
140
65
-
-
-
-
-
-
-
ps
ps
ps
ps
ps
ps
ps
16
16
tIS(base)
AC175
Address and Control input setup time
(VIH/VIL(AC175) levels)
tIS(base)
AC150
Address and Control input setup time
(VIH/VIL(AC150) levels)
45+125
45
65+150
65
16,24
17
DQ and DM input hold time
(VIH/VIL(DC) levels)
tDH(base)
tDS(base)
tIPW
DQ and DM input setup time
(VIH/VIL(AC) levels)
10
10
17
Address and control input pulse width
for each input
560
360
620
400
25
DQ and DM input pulse width for
each input
tDIPW
25
tHZ(DQ)
tLZ(DQ)
DQ high impedance time
DQ low impedance time
DQS,/DQS high impedance time
RL+BL/2 reference
-
225
225
-
250
250
ps
ps
13,14
13,14
-450
-500
tHZ(DQS)
tLZ(DQS)
-
225
225
-
250
250
ps
ps
13,14
DQS,/DQS low impedance time
RL-1 reference
-450
-500
13,14
12,13
DQS,/DQS to DQ skew per group,
per access
tDQSQ
tCCD
tQH
-
4
100
-
4
125
ps
/CAS to /CAS command delay
-
-
-
-
nCK
tCK
(avg)
DQ output hold time from DQS, /DQS
0.38
0.38
12,13
12,13
DQS,/DQS rising edge output access
time from rising CK,/CK
tDQSCK
tDQSS
tDQSH
-225
-0.27
0.45
225
0.27
0.55
-255
-0.25
0.45
255
0.25
0.55
ps
DQS latch rising transitions to
associated clock edges
tCK
(avg)
tCK
(avg)
DQS input high pulse width
27,28
May. 2011
17/39
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