EM44DM1688LBB
2Gb (16M×8Bank×16) Double DATA RATE 2 SDRAM
Features
• JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
• All inputs and outputs are compatible with SSTL_18
interface.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS
• Bust length: 4 and 8.
• Programmable CAS Latency (CL): 5, 7
• Programmable Additive Latency (AL): 0, 1, 2, 3, 4,
5 & 6.
• Write Latency (WL) =Read Latency (RL) -1.
• Read Latency (RL) = Programmable Additive
Latency (AL) + CAS Latency (CL)
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available.
• Off-Chip Driver (OCD) Impedance Adjustment
• On Die Termination (ODT)
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• Average Refresh Period 7.8us
• RoHS Compliance
• High Temperature Self-Refresh rate enable
Description
The EM44DM1688LBB is a high speed Double Date
Rate 2 (DDR2) Synchronous DRAM fabricated with
ultra high performance CMOS process containing
2,147,483,648 bits which organized as 16Mbits x 8
banks by 16 bits. This synchronous device achieves
high speed double-data-rate transfer rates of up to
1066 Mb/sec/pin (DDR2-1066) for general
applications. The chip is designed to comply with the
following key DDR2 SDRAM features: (1) posted
CAS with additive latency, (2) write latency = read
latency -1, (3) Off-Chip Driver (OCD) impedance
adjustment and On Die Termination (4) normal and
weak strength data output driver. All of the control
and address inputs are synchronized with a pair of
externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK
rising and /CK falling). All I/Os are synchronized with
a pair of bidirectional strobes (DQS and /DQS) in a
source synchronous fashion. The address bus is
used to convey row, column and bank address
information in a /RAS and /CAS multiplexing style.
The 2Gb DDR2 device operates with a single power
supply: 1.8V ± 0.1V VDD and VDDQ. Available
package: FBGA-84Ball (with 0.8mm x 0.8mm ball
pitch)
Nov. 2011
2/29
www.eorex.com
EOREX [ EOREX CORPORATION ]
