EM44CM1688LBA
AC Operating Test Characteristics
(VDD=1.8V±0.1V, TA=0°C ~85°C)
Symbol
Parameter
-25
-3
-37
Units
Min.
Max.
0.40
Min.
Max.
0.45
Min.
-0.5
Max.
0.5
tAC
DQ output access from CLK,/CLK
DQS output access from CLK,/CLK
CL low/high level width
-0.40
-0.45
ns
ns
tCK
tDQSCK
tCL,tCH
-0.35
0.48
0.35
0.52
-0.40
0.48
0.40
0.52
-0.45
0.45
0.45
0.55
Clock Cycle Time
tCK
2.5
8
3
8
3.75
0.10
8
ns
CL=6/5/4, Speed= -25/-3/-37
DQ and DM setup time
tDS
tDH
0.05
-
-
0.10
-
-
-
-
ns
ns
DQ and DM hold time
0.125
0.175
0.225
DQ and DM input pulse width for
each input
tDIPW
tHZ
tLZ (DQ)
tLZ (DQS)
tDQSQ
tQHS
0.35
-
-
0.35
-
-
0.35
-
ns
ns
ns
ns
tAC
(max)
tAC
tAC
(max)
tAC
Data out high impedance time from
CLK,/CLK
tAC
(max)
-
tAC
(max)
tAC
2*tAC
(min)
tAC
2*tAC
(min)
tAC
DQ low impedance time from
CLK,/CLK
2*tAC
(min)
(max)
tAC
(max)
tAC
DQS,/DQS low impedance time
from CLK,/CLK
tAC
(min)
(max)
(min)
(max)
(min)
(max)
DQS-DQ skew for associated DQ
signal
-
-
0.20
0.30
0.25
-
-
0.24
0.34
0.25
-
-
0.30
0.40
0.25
ns
ns
tCK
Data hold skew factor
Write command to first latching
DQS transition
tDQSS
-0.25
-0.25
-0.25
tDQSL,tDQSH DQS Low/High input pulse width
0.35
0.20
-
-
0.35
0.20
-
-
0.35
0.20
-
-
tCK
tCK
tDSL,tDSH
DQS input valid window
Mode Register Set command cycle
time
tMRD
2
-
2
-
2
-
tCK
tWPRES
tWPRE
tWPST
Write Preamble setup time
Write Preamble
0
-
-
0
-
-
0
-
-
ns
tCK
tCK
0.35
0.4
0.35
0.4
0.35
0.4
Write Postamble
0.6
0.6
0.6
Address/control input setup time
(fast slew rate)
tIS
0.175
-
0.20
-
0.25
-
ns
Address/control input hold time
(fast slew rate)
tIH
0.25
0.9
-
0.275
0.9
-
0.375
0.9
-
ns
tRPRE
Read Preamble
1.1
1.1
1.1
tCK
Jun. 2010
11/28
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EOREX [ EOREX CORPORATION ]
