EM44CM1688LBB
Extended Mode Register Set EMRS(1 )
The EMRS (1) is written by asserting low on /CS, /RAS, /CAS, /WE,BA1 and high on BA0 ( The DDR2 should
be in all bank pre-charge with CKE already prior to writing into the extended mode register. ) The extended
mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive
latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of
the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after
power-up for proper operation. The mode register set command cycle time (tMRD) must be satisfied to complete
the write operation to the EMRS(1). Mode register contents can be changed using the same command and
clock cycle requirements during normal operation when all banks are in pre-charge state.
BA2 BA1 BA0
A12
Qoff
A11
A10
A9
A8
A7
A6
Rtt
A5
A4
A3
A2
Rtt
A1
A0
RDQS
/DQS
D.I.C.
0
0
1
OCD program
Additive latency
DLL
Qoff (Output Buffer)
Enabled
A12
RDQS
A11
/DQS
Enable
Disable
A10
DLL
A0
0
enable
Disable
Enable
0
1
0
1
Enable
Disable
0
1
Disabled
1
Output Driver
A1
Impedance Control
Normal (100%)
Weak (60%)
0
1
OCD Calibration Program
OCD Calibration mode exit
Drive (1)
A9
0
A8
0
A7
0
Rtt
A6
0
A2
0
0
0
1
ODT Disable
75 ohm
Drive (0)
0
1
0
0
1
Adjust mode (*1)
1
0
0
150 ohm
50 ohm
1
0
OCD Calibration default (*2)
1
1
1
1
1
*1: When adjust mode is issued, AL from previously set value
must be applied.
*2: After setting to default, OCD mode needs to be exited by
Additive Latency
A5
A4
A3
setting A9-A7 to 000. Refer to the section Off-Chip Driver (OCD)
impedance adjustment for detail information
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
MRS Mode
MRS
BA1
0
BA0
0
2
3
EMRS(1)
0
1
4
EMRS(2)
1
0
5
6
EMRS(3) Reserved
1
1
Reserved
Nov. 2010
25/29
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