EM44CM1688LBB
AC Operating Test Characteristics
(VDD=1.8V±0.1V, TA=0°C ~70°C)
-25 (DDR2-800)
-3 (DDR2-667)
Units
Symbol
Parameter
Min.
Max.
Min.
Max.
tAC
DQ output access from CLK,/CLK
DQS output access from CLK,/CLK
CL low/high level width
Clock Cycle Time
-0.40
-0.35
0.48
0.40
0.35
0.52
-0.45
-0.40
0.48
0.45
0.40
0.52
ns
ns
tCK
tDQSCK
tCL,tCH
tCK
2.5
8
3
8
ns
CL=5, Speed= -25/-3
tDS
tDH
DQ and DM setup time
DQ and DM hold time
0.05
-
-
0.10
-
-
ns
ns
0.125
0.175
DQ and DM input pulse width for each
input
tDIPW
tHZ
0.35
-
0.35
-
ns
ns
tAC
tAC
Data out high impedance time from
CLK,/CLK
-
-
(max)
(max)
2*tAC
tAC
2*tAC
tAC
tLZ (DQ)
DQ low impedance time from CLK,/CLK
ns
ns
(min)
(max)
(min)
(max)
tAC
tAC
tAC
tAC
DQS,/DQS low impedance time from
CLK,/CLK
tLZ (DQS)
(min)
(max)
(min)
(max)
tDQSQ
tQHS
DQS-DQ skew for associated DQ signal
Data hold skew factor
-
0.20
-
0.24
ns
ns
-
0.30
-
0.34
Write command to first latching DQS
transition
tDQSS
-0.25
0.25
-0.25
0.25
tCK
tDQSL,tDQSH DQS Low/High input pulse width
0.35
0.20
2
-
0.35
0.20
2
-
tCK
tCK
tCK
ns
tCK
tCK
tDSL,tDSH
tMRD
DQS input valid window
Mode Register Set command cycle time
Write Preamble setup time
Write Preamble
-
-
-
-
-
tWPRES
tWPRE
tWPST
0
0
-
0.35
0.4
-
0.35
0.4
-
Write Postamble
0.6
0.6
Address/control input setup time (fast
slew rate)
tIS
0.175
-
0.20
-
ns
Address/control input hold time
(fast slew rate)
tIH
0.25
0.9
-
0.275
0.9
-
ns
tRPRE
Read Preamble
1.1
1.1
tCK
Nov. 2010
12/29
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EOREX [ EOREX CORPORATION ]
