eorex
EM44AM1684LBC
Initialization
The following sequence is required for power-up and initialization and is shown in below Figure:
1. Apply power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may
be undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODTpin.
- VDD,VDDL and VDDQ are driven from a single power converter output, AND
VTT is limited to 0.95 V max, AND VREF tracks VDDQ/2
or
- Apply VDD before or at the same time as VDDL; Apply VDDL before or at the same time as VDDQ;
Apply VDDQ before or at the same time as VTT & VREF.
at least one of these two sets of conditions must be met.
2. Start clock (CK, /CK) and maintain stable power and clock condition for a minimum of 200 µs.
3. Apply NOP or Deselect commands & take CKE high.
4. Wait minimum of 400ns, then issue a Precharge-all command.
5. Issue Reserved command EMRS(2) or EMRS(3).
6. Issue EMRS(1) command to enable DLL. (A0=0 and BA0=1 and BA1=0)
7. Issue MRS command (Mode Register Set) for "DLL reset". (A8=1 and BA0=BA1=0)
8. Issue Precharge-All command.
9. Issue 2 or more Auto-Refresh commands.
10. Issue a MRS command with low on A8 to initialize device operation. (without resetting the DLL)
11. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If
OCD calibration is not used, EMRS OCD Default command (A9=A8=A7=1) followed by EMRS(1) OCD
Calibration Mode Exit command (A9=A8=A7=0) must be issued with other parameters of EMRS(1).
12. The DDR2 SDRAM is now initialized and ready for normal operation.
Jul. 2006
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EOREX [ EOREX CORPORATION ]
