EM42CM1684RTA
AC Operating Test Characteristics
(V
DD
=2.5V±0.2V)
Symbol
t
DQCK
t
DQSCK
t
CL
,t
CH
t
CK
t
DH
,t
DS
t
DIPW
t
HZ
,t
LZ
t
DQSQ
t
DQSS
t
DSL
,t
DSH
t
MRD
t
WPRES
t
WPST
t
IH
,t
IS
t
RPRE
t
DSH
t
DSS
Parameter
DQ output access from CLK,/CLK
DQS output access from CLK,/CLK
CL low/high level width
Clock Cycle Time
DQ and DM hold/setup time
DQ and DM input pulse width for each input
Data out high/low impedance time from
CLK,/CLK
DQS-DQ skew for associated DQ signal
Write command to first latching DQS
transition
DQS input valid window
Mode Register Set command cycle time
Write Preamble setup time
Write Postamble
Address/control input hold/setup time (Slow)
Address/control input hold/setup time (Fast)
Read Preamble
DQS falling edge from CLK rising, hold time
DQS falling edge to CLK rising, setup time
CL=3
-6
Min.
-0.7
-0.6
0.45
6
0.45
1.75
-0.7
-
0.75
0.35
2
0
0.4
0.8
0.75
0.9
0.2
0.2
Max.
0.7
0.6
0.55
12
-
-
0.7
0.4
1.25
-
-
-
0.6
-
-
1.1
-
-
Min.
-0.75
-0.75
0.45
7.5
0.5
1.75
-0.75
-
0.75
0.35
2
0
0.4
1
0.9
0.9
0.2
0.2
-75
Max.
0.75
0.75
0.55
12
-
-
0.75
0.5
1.25
-
-
-
0.6
-
-
1.1
-
-
Units
ns
ns
t
CK
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
ns
t
CK
ns
ns
t
CK
t
CK
t
CK
Jan. 2012
9/22
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EOREX [ EOREX CORPORATION ]
