EM42CM1684RTA
AC Operating Test Characteristics
(VDD=2.5V±0.2V)
-6
-75
Symbol
Parameter
Units
Min.
-0.7
Max.
0.7
Min.
Max.
0.75
tDQCK
tDQSCK
tCL,tCH
tCK
DQ output access from CLK,/CLK
DQS output access from CLK,/CLK
CL low/high level width
-0.75
ns
ns
tCK
ns
ns
ns
-0.6
0.45
6
0.6
0.55
12
-
-0.75
0.45
7.5
0.75
0.55
12
-
Clock Cycle Time
CL=3
tDH,tDS
tDIPW
DQ and DM hold/setup time
0.45
1.75
0.5
DQ and DM input pulse width for each input
-
1.75
-
Data out high/low impedance time from
CLK,/CLK
tHZ,tLZ
tDQSQ
tDQSS
-0.7
-
0.7
0.4
-0.75
-
0.75
0.5
ns
ns
tCK
DQS-DQ skew for associated DQ signal
Write command to first latching DQS
transition
0.75
1.25
0.75
1.25
tDSL,tDSH
tMRD
tWPRES
tWPST
DQS input valid window
0.35
2
-
0.35
2
-
tCK
tCK
ns
tCK
ns
ns
tCK
tCK
tCK
Mode Register Set command cycle time
Write Preamble setup time
-
-
0
-
0
-
Write Postamble
0.4
0.8
0.75
0.9
0.2
0.2
0.6
0.4
1
0.6
Address/control input hold/setup time (Slow)
Address/control input hold/setup time (Fast)
Read Preamble
-
-
tIH,tIS
-
1.1
-
0.9
0.9
0.2
0.2
-
1.1
-
tRPRE
tDSH
tDSS
DQS falling edge from CLK rising, hold time
DQS falling edge to CLK rising, setup time
-
-
Jan. 2012
www.eorex.com
9/22
EOREX [ EOREX CORPORATION ]
