EM42BM1684RTC
Pin Description (Simplified)
Pin
45,46
Name
CLK,/CLK
Function
(System Clock)
Clock input active on the Positive rising edge
except for DQ and DM are active on both edge of the DQS. CLK
and /CLK are differential clock inputs.
(Chip Select)
/CS enables the command decoder when”L” and
disable the command decoder when “H”. The new commands are
over- Looked when the command decoder is disabled but previous
operation will still continue.
(Clock Enable)
Activates the CLK when “H” and deactivates when
“L”. When deactivate the clock, CKE low signifies the power down
or self refresh mode.
(Address)
Row address (A0 to A12) and Column address (CA0 to
CA9) are multiplexed on the same pin. CA10 defines auto
precharge at Column address.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive
rising edge of the CLK with /RAS “L”. Enables row access &
pre-charge.
(Column Address Strobe)
Latches Column Addresses on the
positive rising edge of the CLK with /CAS low. Enables column
access.
(Write Enable)
Latches Column Addresses on the positive rising
edge of the CLK with /CAS low. Enables column access.
(Data Input/Output)
Data Inputs and Outputs are synchronized
with both edges of DQS.
(Data Input/Output Mask)
DM controls data inputs. LDM
corresponds to the data on DQ0~DQ7.UDM corresponds to the
data on DQ8~DQ15.
(Data Input/Output)
Data inputs and outputs are multiplexed on
the same pin.
(Power Supply/Ground)
V
DD
and V
SS
are power supply pins for
internal circuits.
(Power Supply/Ground)
V
DDQ
and V
SSQ
are power supply pins for
the output buffers.
(No Connection/Reserved for Future Use)
This pin is
recommended to be left No Connection on the device.
(Input)
SSTL-2 Reference voltage for input buffer.
24
/CS
44
CKE
28~32,35~42
A0~A12
26, 27
23
BA0, BA1
/RAS
22
21
16/51
20/47
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
1,18,33/ 34,48,66
3, 9, 15, 55.61/ 6,
12, 52, 58,64
14,17,19,25,43,
50,53
49
/CAS
/WE
LDQS/UDQS
LDM/UDM
DQ0~DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC/RFU
V
REF
Apr. 2012
5/23
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