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EM42BM1684RBA-6FE 参数 Datasheet PDF下载

EM42BM1684RBA-6FE图片预览
型号: EM42BM1684RBA-6FE
PDF下载: 下载PDF文件 查看货源
内容描述: [DRAM]
分类和应用: 动态存储器
文件页数/大小: 23 页 / 403 K
品牌: EOREX [ EOREX CORPORATION ]
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EM42BM1684RBA  
Pin Description (Simplified)  
Pin  
Name  
Function  
(System Clock) Clock input active on the Positive rising edge  
except for DQ and DM are active on both edge of the DQS.  
CLK and /CLK are differential clock inputs.  
G2, G3  
CLK,/CLK  
(Chip Select) /CS enables the command decoder when”L” and  
disable the command decoder when “H”. The new commands  
are over- Looked when the command decoder is disabled but  
previous operation will still continue.  
H8  
H3  
/CS  
(Clock Enable) Activates the CLK when “H” and deactivates  
when “L”. When deactivate the clock, CKE low signifies the  
power down or self refresh mode.  
CKE  
(Address) Row address (A0 to A12) and Column address  
(CA0 to CA9) are multiplexed on the same pin. CA10 defines  
auto precharge at Column address.  
K7,L8,L7,M8,M2,L3,  
L2,K3,K2,J3,K8,J2,H2  
A0~A12  
BA0, BA1  
/RAS  
(Bank Address) Selects which bank is to be active.  
J8, J7  
H7  
(Row Address Strobe) Latches Row Addresses on the  
positive rising edge of the CLK with /RAS “L”. Enables row  
access & pre-charge.  
(Column Address Strobe) Latches Column Addresses on the  
positive rising edge of the CLK with /CAS low. Enables column  
access.  
G8  
/CAS  
(Write Enable) Latches Column Addresses on the positive  
rising edge of the CLK with /CAS low. Enables column access.  
G7  
/WE  
(Data Input/Output) Data Inputs and Outputs are  
synchronized with both edges of DQS.  
E7, E3  
LDQS/UDQS  
(Data Input/Output Mask) DM controls data inputs. LDM  
corresponds to the data on DQ0~DQ7.UDM corresponds to  
the data on DQ8~DQ15.  
F7, F3  
LDM/UDM  
A8,B9,B7,C9,C7,  
D9,D7,E9,E1,D3,  
D1,C3,C1,B3,B1,A2  
(Data Input/Output) Data inputs and outputs are multiplexed  
on the same pin.  
DQ0~DQ15  
(Power Supply/Ground) VDD and VSS are power supply pins  
for internal circuits.  
A7,F8,M7/A3,F2,M3  
VDD/VSS  
A9,B2,C8,D2,E8/  
A1,B8,C2,D8,E2  
(Power Supply/Ground) VDDQ and VSSQ are power supply pins  
for the output buffers.  
VDDQ/VSSQ  
(No Connection/Reserved for Future Use) This pin is  
recommended to be left No Connection on the device.  
F9  
F1  
NC/RFU  
VREF  
(Input) SSTL-2 Reference voltage for input buffer.  
Dec. 2010  
5/23  
www.eorex.com  
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