eorex
EM42AM3284LBC
Extended Mode Register Set ( EMRS )
The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The
DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode
register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going
low is written in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used
for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0
must be set to low for proper EMRS operation.
Jun. 2009
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