eorex
EM42BM1684RTA
Extended Mode Register Set ( EMRS )
The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode
register is not defined, so the extended mode register must be written after power up for enabling or
disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on
BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended
mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE
going low is written in the extended mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. A0
is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and
BA0 must be set to low for proper EMRS operation.
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU :Must be set as 0
/QFC
D.I.C
0
1
DLL
DLL
QFC control
Disable
A2
0
A0
0
Enable
Disable
Enable
1
1
Output Driver
Impedance Control
A1
Normal
Weak
0
1
BA0
MRS Mode
0
1
MRS
EMRS
Jul. 2006
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EOREX [ EOREX CORPORATION ]
