eorex
Preliminary
EM42BM1684LBB
Pin Description (Simplified)
Pin
Name
Function
(System Clock)
Clock input active on the Positive rising edge except for DQ and
DM are active on both edge of the DQS.
CLK and /CLK are differential clock inputs.
(Chip Select)
G2,G3
CLK,/CLK
/CS enables the command decoder when ”L” and disable the
command decoder when “H”.The new command are over-
Looked when the command decoder is disabled but previous
operation will still continue.
H8
H1
/CS
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
When deactivate the clock,CKE low signifies the power down or
self refresh mode.
CKE
(Address)
K7,L8,L7,M8,M2,
L3,L2,K3,K2,J3,K8,
J2,H2
Row address (A0 to A12) and Calumn address (CA0 to CA9) are
multiplexed on the same pin.
CA10 defines auto precharge at Calumn address.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK with
/RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
A0~12
J8,J7
H7
BA0, BA1
/RAS
G8
/CAS
/WE
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Data Input/Output)
G7
LDQS,
UDQS
E7,E3
F7,F8
Data Inputs and Outputs are synchronized with both edge of DQS.
(Data Input/Output Mask)
LDM,UDM DM controls data inputs.LDM corresponds to the data on
DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15……..
A8,B9,B7,C9
C7,D9,D7,E9
E1,D3,D1,C3
C1,B3,B1,A2
A7,F8,M7/
A3,F2,M3
A9,B1,C8,D2,E8 /
A1,B8,C2,D8,E2,
(Data Input/Output)
DQ0~15
Data inputs and outputs are multiplexed on the same pin.
(Power Supply/Ground)
VDD/VSS
V
DD and VSS are power supply pins for internal circuits.
(Power Supply/Ground)
DDQ and VSSQ are power supply pins for the output buffers.
VDDQ/VSSQ
V
(No Connection/Reserved for Future Use)
This pin is recommended to be left No Connection on the device.
F1,F9
NC/RFU
Jul. 2006
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