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EN29LV320T-70TIP 参数 Datasheet PDF下载

EN29LV320T-70TIP图片预览
型号: EN29LV320T-70TIP
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位( 4096K ×8位/ 2048K ×16位)闪存引导扇区快闪记忆体, CMOS 3.0伏只 [32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 49 页 / 420 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN29LV320  
DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to  
return the device to reading array data.  
DQ3: Sector Erase Timer  
After writing a sector erase command sequence, the output on DQ3 can be checked to determine  
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip  
erase command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not  
support multiple sector erase (continuous sector erase) command sequences so it is not very  
meaningful since it immediately shows as a “1” after the first 30h command. Future devices may  
support this feature.  
DQ2: Erase Toggle Bit II  
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively  
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-  
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command  
sequence. DQ2 toggles when the system reads at addresses within those sectors that have been  
selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2  
cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by  
comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot  
distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and  
mode information. Refer to the following table to compare outputs for DQ2 and DQ6.  
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.  
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit  
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical  
form.  
Reading Toggle Bits DQ6/DQ2  
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading  
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is  
toggling. Typically, a system would note and store the value of the toggle bit after the first read. After  
the second read, the system would compare the new value of the toggle bit with the first. If the  
toggle bit is not toggling, the device has completed the program or erase operation. The system can  
read array data on DQ7–DQ0 on the following read cycle.  
However, after the initial two read cycles, the system determines that the toggle bit is still toggling.  
And the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is,  
the system should then determine again whether the toggle bit is toggling, since the toggle bit may  
have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has  
successfully completed the program or erase operation. If it is still toggling, the device did not  
complete the operation successfully, and the system must write the reset command to return to  
reading array data.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.essi.com.tw  
24  
Rev. E, Issue Date: 2006/05/16  
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