EN29F010
Table 5. EN29F010 Command Definitions
1st
2nd
3rd
4th
5th
6th
Command
Write
Write Cycle
Sequence
Write Cycle
Write Cycle
Write Cycle
Write Cycle Write Cycle
Cycles
Req’d
Read/Reset
Addr Data
RA RD
XXXh F0h
555h AAh 2AAh 55h 555h F0h
555h AAh 2AAh 55h 555h 90h
555h AAh 2AAh 55h 555h 90h
555h AAh 2AAh 55h 555h 90h
555h AAh 2AAh 55h 555h A0h
555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h
xxxh B0h
xxxh 30h
Addr
Data Addr Data Addr Data Addr Data Addr Data
1
1
4
Read
Reset
Read/Reset
RA
RD
000h/ 7Fh/
AutoSelect
Manufacturer ID
AutoSelect Device ID
4
4
4
100h 1Ch
01h
20h
BA & 00h/
AutoSelect Sector
Protect Verify
02h
PA
01h
PD
4
6
6
1
1
Byte Program
Chip Erase
Sector Erase
BA
30h
Sector Erase Suspend
Sector Erase Resume
Notes:
RA = Read Address: address of the memory location to be read. This one is a read cycle.
RD = Read Data: data read from location RA during Read operation. This one is a read cycle.
PA = Program Address: address of the memory location to be programmed
PD = Program Data: data to be programmed at location PA
BA = Sector Address: address of the Sector to be erased. Address bits A16-A14 uniquely select any Sector.
The data is 00h for an unprotected sector and 01h for a protected sector.
Byte Programming Command
Programming the EN29F010 is performed on a byte-by-byte basis using a four bus-cycle operation
(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).
When the program command is executed, no additional CPU controls or timings are necessary. An
internal timer terminates the program operation automatically. Address is latched on the falling edge
of
or
, whichever is last; data is latched on the rising edge of
or
CE
, whichever is first.
W E
CE
W E
The program operation is completed when EN29F010 returns the equivalent data to the
programmed location.
Programming status may be checked by sampling data on DQ7 (
polling) or on DQ6 (toggle
bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is
exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read
mode.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations. The Command Definitions table shows the
address and data requirements for the chip erase command sequence.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/10/20
8
or modifications due to changes in technical specifications.
EON [ EON SILICON SOLUTION INC. ]
