EN29F002A / EN29F002AN
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
Description
Read Cycle Time
JEDEC
Standard
Test Setup
-45
45
-55
-70
70
-90
90
Unit
ns
Min
55
tAVAV
tRC
Max
45
55
70
90
ns
Address to Output Delay
tAVQV
tACC
CE = VIL
= VIL
OE
Max
Max
Max
Max
Min
45
25
10
10
0
55
30
15
15
0
70
30
20
20
0
90
35
20
20
0
ns
ns
ns
ns
ns
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tCE
tOE
tDF
tDF
tOH
OE = VIL
Output Enable to Output High Z
Output Hold Time from
Addresses,
or ,
CE OE
whichever occurs first
Max
20
20
20
20
µs
tReady
Pin Low to Read
RESET
Mode (n/a for EN29F002AN)
Notes:
For -45,-55
Vcc = 5.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
For all others:
Vcc = 5.0V ± 10%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
22
Rev. A, Issue Date: 2003/03/26
EON [ EON SILICON SOLUTION INC. ]
