EN25S10
MEMORY ORGANIZATION
The memory is organized as:
z
z
131,072 bytes
Uniform Sector Architecture
4 blocks of 32-Kbyte
32 sectors of 4-Kbyte
512 pages (256 bytes each)
z
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block
Sector
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Address range
01F000h
01E000h
01D000h
01C000h
01B000h
01A000h
019000h
018000h
017000h
016000h
015000h
014000h
013000h
012000h
011000h
010000h
00F000h
00E000h
00D000h
00C000h
00B000h
00A000h
009000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
01FFFFh
01EFFFh
01DFFFh
01CFFFh
01BFFFh
01AFFFh
019FFFh
018FFFh
017FFFh
016FFFh
015FFFh
014FFFh
013FFFh
012FFFh
011FFFh
010FFFh
00FFFFh
00EFFFh
00DFFFh
00CFFFh
00BFFFh
00AFFFh
009FFFh
008FFFh
007FFFh
006FFFh
005FFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
3
2
1
0
8
7
6
5
4
3
2
1
0
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
5
Rev. F, Issue Date: 2011/11/07
EON [ EON SILICON SOLUTION INC. ]
