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EN25S10 参数 Datasheet PDF下载

EN25S10图片预览
型号: EN25S10
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位1.8V串行闪存与4K字节扇区制服 [1 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector]
分类和应用: 闪存
文件页数/大小: 34 页 / 530 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25S10  
Read Status Register (RDSR) (05h)  
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status  
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in  
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress  
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register  
continuously, as shown in Figure 7.  
Figure 7. Read Status Register Instruction Sequence Diagram  
Table 6. Status Register Bit Locations  
S7  
OTP_LOCK  
S6  
S5  
S4  
S3  
S2  
S1  
S0  
SRP  
Status Register  
Protect  
BP2  
BP1  
BP0  
WEL  
WIP  
(Write In  
Progress bit)  
bit  
(Block Protected (Block Protected (Block Protected (Write Enable  
bits)  
bits)  
bits)  
Latch)  
(note 1)  
Reserved Reserved  
bits bits  
1 = write  
enable  
0 = not write 0 = not in write  
1 = write  
operation  
1 = status  
register write  
disable  
1 = OTP  
sector is  
protected  
(note 2 & 3)  
(note 2 & 3)  
(note 2 & 3)  
enable  
operation  
Non-volatile bit  
Non-volatile bit Non-volatile bit Non-volatile bit  
volatile bit  
volatile bit  
Note :  
1. In OTP mode, SRP bit is served as OTP_LOCK bit.  
2. After power-up, BP2, BP1 and BP0 are set to defaults 1 and protect full memory.  
3. See the table 3 “Protected Area Sizes Sector Organization”.  
The status and control bits of the Status Register are as follows:  
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status  
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such  
cycle is in progress.  
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.  
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is  
reset and no Write Status Register, Program or Erase instruction is accepted.  
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of  
the area to be software protected against Program and Erase instructions. These bits are written with  
the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0)  
bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc.,  
www.eonssi.com  
12  
Rev. F, Issue Date: 2011/11/07