EN25Q16A
Figure 9.1 Read Status Register Instruction Sequence under EQPI Mode
Table 6. Status Register Bit Locations
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Status
Register
Protect
WIP
(Write In
Progress bit)
(Note 3)
OTP_LOCK
BP3
BP2
BP1
BP0
WEL
(Write Enable
Latch)
WPDIS
(WP# disable)
bit
(Block
(Block
(Block
(Block
Protected bits) Protected bits) Protected bits) Protected bits)
(note 1)
1 = WP#
disable
0 = WP#
enable
1 = write
enable
0 = not write 0 = not in write
1 = write
operation
1 = status
register write sector is
disable protected
1 = OTP
(note 2)
(note 2)
(note 2)
(note 2)
enable
operation
Non-volatile bit
Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit
volatile bit
volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
18
Rev. E, Issue Date: 2011/07/14
EON [ EON SILICON SOLUTION INC. ]
