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EN25Q16A-104HIP 参数 Datasheet PDF下载

EN25Q16A-104HIP图片预览
型号: EN25Q16A-104HIP
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位串行闪存与4K字节扇区制服 [16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector]
分类和应用: 闪存
文件页数/大小: 53 页 / 1059 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25Q16A  
Table 3. Protected Area Sizes Sector Organization  
Status Register Content  
Memory Content  
BP3 BP2 BP1 BP0  
Protect Areas  
Addresses  
None  
Density(KB)  
None  
Portion  
Bit  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
None  
None  
Block 0 to 30  
Block 0 to 29  
Block 0 to 27  
Block 0 to 23  
Block 0 to 15  
All  
All  
None  
Block 31 to 1  
Block 31 to 2  
Block 31 to 4  
Block 31 to 8  
000000h-1EFFFFh 1984KB  
000000h-1DFFFFh 1920KB  
000000h-1BFFFFh 1792KB  
000000h-17FFFFh 1536KB  
000000h-0FFFFFh 1024KB  
000000h-1FFFFFh 2048KB  
000000h-1FFFFFh 2048KB  
Lower 31/32  
Lower 30/32  
Lower 28/32  
Lower 24/32  
Lower 16/32  
All  
All  
None  
None  
None  
1FFFFFh-010000h 1984KB  
1FFFFFh-020000h 1920KB  
1FFFFFh-040000h 1792KB  
1FFFFFh-080000h 1536KB  
Upper 31/32  
Upper 30/32  
Upper 28/32  
Upper 24/32  
Upper 16/32  
All  
Block 31 to 16 1FFFFFh-100000h 1024KB  
All  
All  
1FFFFFh-000000h 2048KB  
1FFFFFh-000000h 2048KB  
All  
INSTRUCTIONS  
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial  
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is  
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,  
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).  
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction  
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by  
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has  
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed  
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output  
FAST_READ (EBh), Read Status Register (RDSR) or Release from Deep Power-down, and Read  
Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence.  
Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.  
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write  
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)  
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction  
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock  
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at  
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.  
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down  
(RES ) minimum number of bytes specified has to be given, without which, the command will be  
ignored.  
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1  
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any  
less or more will cause the command to be ignored.  
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase  
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues  
unaffected.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc.,  
www.eonssi.com  
10  
Rev. E, Issue Date: 2011/07/14