EN25Q128
Table 3. Protected Area Sizes Sector Organization
Status Register Content
Memory Content
BP3 BP2 BP1 BP0
Protect Areas
Addresses
None
000000h-FEFFFFh 16320KB
000000h-FDFFFFh 16256KB
000000h-FBFFFFh 16128KB
Density(KB)
None
Portion
Bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
None
None
Block 0 to 254
Block 0 to 253
Block 0 to 251
Block 0 to 247
Block 0 to 239
Block 0 to 223
All
Lower 255/256
Lower 254/256
Lower 252/256
Lower 248/256
Lower 240/256
Lower 224/256
All
000000h-F7FFFFh
15872KB
000000h-EFFFFFh 15360KB
000000h-DFFFFFh 14336KB
000000h-FFFFFFh 16384KB
None
None
None
None
Block 255 to 1
Block 255 to 2
Block 255 to 4
Block 255 to 8
Block 255 to 16 FFFFFFh-100000h 15360KB
Block 255 to 32 FFFFFFh-200000h 14336KB
FFFFFFh-010000h 16320KB
FFFFFFh-020000h 16256KB
FFFFFFh-040000h 16128KB
FFFFFFh-080000h 15872KB
Upper 255/256
Upper 254/256
Upper 252/256
Upper 248/256
Upper 240/256
Upper 224/256
All
All
FFFFFFh-000000h 16384KB
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR) or Release from Deep Power-down, and Read
Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
14
Rev. J, Issue Date: 2011/09/19
EON [ EON SILICON SOLUTION INC. ]
