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EN25F05-75VIP 参数 Datasheet PDF下载

EN25F05-75VIP图片预览
型号: EN25F05-75VIP
PDF下载: 下载PDF文件 查看货源
内容描述: 512 Kbit的串行闪存与4KB的部门统一 [512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector]
分类和应用: 闪存
文件页数/大小: 31 页 / 422 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25F05  
Table 11. 75MHz AC Characteristics  
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)  
Min  
Typ  
Max  
Unit  
Symbol  
Alt  
fC  
Parameter  
Serial Clock Frequency for:  
FAST_READ, PP, SE, BE, DP, RES, WREN,  
WRDI, WRSR  
FR  
D.C.  
75  
MHz  
fR  
Serial Clock Frequency for READ, RDSR, RDID  
Serial Clock High Time  
D.C.  
6
66  
MHz  
ns  
1
tCLH  
1
tCLL  
Serial Clock Low Time  
6
ns  
2
tCLCH  
Serial Clock Rise Time (Slew Rate)  
Serial Clock Fall Time (Slew Rate)  
CS# Active Setup Time  
0.1  
0.1  
5
V / ns  
V / ns  
ns  
2
tCHCL  
tSLCH  
tCHSH  
tSHCH  
tCHSL  
tSHSL  
tCSS  
CS# Active Hold Time  
5
ns  
CS# Not Active Setup Time  
CS# Not Active Hold Time  
5
ns  
5
ns  
tCSH  
tDIS  
tHO  
CS# High Time  
100  
ns  
2
tSHQZ  
Output Disable Time  
6
ns  
tCLQX  
tDVCH  
tCHDX  
tHLCH  
tHHCH  
tCHHH  
tCHHL  
Output Hold Time  
0
2
5
5
5
5
5
ns  
tDSU  
tDH  
Data In Setup Time  
ns  
Data In Hold Time  
ns  
HOLD# Low Setup Time ( relative to CLK )  
HOLD# High Setup Time ( relative to CLK )  
HOLD# Low Hold Time ( relative to CLK )  
HOLD# High Hold Time ( relative to CLK )  
HOLD# Low to High-Z Output  
HOLD# High to Low-Z Output  
Output Valid from CLK  
ns  
ns  
ns  
ns  
2
tHZ  
tLZ  
tV  
tHLQZ  
6
6
6
ns  
2
tHHQZ  
ns  
tCLQV  
ns  
3
tWHSL  
Write Protect Setup Time before CS# Low  
Write Protect Hold Time after CS# High  
CS# High to Deep Power-down Mode  
20  
ns  
3
tSHWL  
100  
ns  
2
tDP  
3
3
µs  
CS# High to Standby Mode without Electronic  
Signature read  
2
tRES1  
µs  
µs  
CS# High to Standby Mode with Electronic  
Signature read  
2
tRES2  
1.8  
tW  
Write Status Register Cycle Time  
Page Programming Time  
Sector Erase Time  
10  
1.5  
0.15  
0.8  
1
15  
5
ms  
ms  
s
tPP  
tSE  
tBE  
0.3  
2
Block Erase Time  
s
tCE  
2
s
Chip Erase Time  
Note: 1. T  
+ T  
must be greater than or equal to 1/ FCLK  
CLKL  
CLKH  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.essi.com.tw  
24  
Rev. B, Issue Date: 2008/06/23  
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