EM6323/24
Functional Description
V
DD
MR
WDI
High Impedance
RESET
t < t
WD
t
POR
t > t
WD
t
POR
t
POR
Fig. 14
Reset Outputs
A microprocessor (µP) reset input starts the
µP
in a
known state. The EM6323/24
µP
supervisory circuits
assert a reset to prevent code-execution errors during
power-up, power-down, and brownout conditions.
RESET
is guaranteed to be a logic low for V
DD
down to 0.9V.
Once V
DD
exceeds the reset threshold, an internal timer
keeps
RESET
low for the specified reset timeout period
(t
POR
); after this interval,
RESET
returns high.
If a brownout condition occurs (V
DD
dips below the reset
threshold),
RESET
goes low. Each time
RESET
is
asserted it stays low for the reset timeout period. Any
time V
DD
goes below the reset threshold the internal
timer restarts.
RESET
is the inverse of RESET.
Manual Reset Input (EM6323 only)
A logic low on
MR
asserts a reset. Reset remains
asserted while
MR
is low, and for t
POR
(200ms nominal for
EM6323 C-G-L-Q) after it returns high.
MR
has an
internal 30k
Ω
pull-up resistor, so it can be left open if
unused. This input can be driven with CMOS logic levels
or with open-drain outputs. Connect a normally open
momentary switch from
MR
to V
SS
to create a manual-
reset function; debounce circuitry is integrated. If
MR
is
driven from long cable or the device is used in a noisy
environment, connect a 0.1
µ
F capacitor from
MR
to V
SS
to provide additional noise immunity (stronger external
additional pull-up resistor can also be added).
Copyright
©
2006, EM Microelectronic-Marin SA
03/06 - rev.H
8
www.emmicroelectronic.com
EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
