EM6323/24
Functional Description
VDD
MR
WDI
High Impedance
RESET
t < tWD
t > tWD
tPOR
tPOR
tPOR
Fig. 14
Reset Outputs
Manual Reset Input (EM6323 only)
A microprocessor (µP) reset input starts the µP in a
known state. The EM6323/24 µP supervisory circuits
assert a reset to prevent code-execution errors during
A logic low on MR asserts a reset. Reset remains
asserted while MR is low, and for tPOR (200ms nominal for
EM6323 C-G-L-Q) after it returns high. MR has an
power-up, power-down, and brownout conditions.
RESET
internal 30k
Ω pull-up resistor, so it can be left open if
is guaranteed to be a logic low for VDD down to 0.9V.
Once VDD exceeds the reset threshold, an internal timer
unused. This input can be driven with CMOS logic levels
or with open-drain outputs. Connect a normally open
keeps
low for the specified reset timeout period
RESET
momentary switch from MR to VSS to create a manual-
(tPOR); after this interval,
returns high.
RESET
reset function; debounce circuitry is integrated. If MR is
driven from long cable or the device is used in a noisy
If a brownout condition occurs (VDD dips below the reset
threshold), goes low. Each time is
RESET
RESET
environment, connect a 0.1µF capacitor from MR to VSS
to provide additional noise immunity (stronger external
additional pull-up resistor can also be added).
asserted it stays low for the reset timeout period. Any
time VDD goes below the reset threshold the internal
timer restarts.
is the inverse of RESET.
RESET
8
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Copyright
03/06 - rev.H
© 2006, EM Microelectronic-Marin SA
EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
