R
EM6152
of the POR delay. A TCL pulse will have no effect until this
power-on-reset delay is completed. When the risk exists that
TCL temporarily floats, e.g. during TPOR, a pull-up to
VOUTPUT is required on that pin. After the POR delay has
elapsed, RES goes inactive and the watchdog timer starts
acting. If no TCL pulse occurs, RES goes active low for a
short time TWDR after each closed and open window period.
A TCL pulse coming during the open window clears the
watchdog timer. When the TCL pulse occurs too early
(during the closed window), RES goes active and a new
timeout sequence starts. A voltage drop below the VREF
level for longer than typically 3μs overrides the timer and
immediately forces RES active and EN inactive. Any
further TCL pulse has no effect until the next power-up
sequence has completed.
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the processor.
If the user’s software does not send a pulse to the TCL
input within the programmed open window timeout period a
short watchdog RES pulse is generated which is equal to
TWDR (see Fig. 6).
With the open window constraint, new security is added to
conventional watchdogs by monitoring both software cycle
time and execution. Should software clear the watchdog too
quickly (incorrect cycle time) or too slowly (incorrect
execution) it will cause the system to be reset. If software is
stuck in a loop which includes the routine to clear the
watchdog then a conventional watchdog would not make a
system reset even though the software is malfunctioning;
the circuit would make a system reset because the
watchdog would be cleared too quickly.
Enable - EN Output
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves of
period TWDRP = TCW + TOW + TWDR. The watchdog will remain
in this state until the next TCL falling edge appears during
an open window, or until a fresh power-up sequence. The
system enable output, EN , can be used to prevent critical
control functions being activated in the event of the system
going into this failure mode (see section “Enable-EN
Output”).
The system enable output, EN , is inactive always when
RES is active and remains inactive after a RES pulse until
the watchdog is serviced correctly 3 consecutive times (i.e.
the TCL pulse must come in the open window). After three
consecutive services of the watchdog with TCL during the
open window, the EN goes active low.
A malfunctioning system would be repeatedly reset by the
watchdog. In a conventional system critical motor controls
could be energized each time reset goes inactive (time
allowed for the system to restart) and in this way the
electrical motors driven by the system could function out of
control. The circuit prevents the above failure mode by using
the EN output to disable the motor controls until software
has successfully cleared the watchdog three times (i.e. the
system has correctly re-started after a reset condition).
The RES output must be pulled up to VOUTPUT even if the
output is not used by the system (see Fig 8).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated
by the sequence of events shown in Fig. 6. On power-up,
when the voltage at VIN reaches VREF, the power-on-reset,
POR, delay is initialized and holds RES active for the time
Typical Application
Unregulated
Voltage
Regulated Voltage (5V)
Address decoder
INPUT OUTPUT
+
EM6152
R1
100nF 22uF
VIN
ROSC
TCL
RES
22uF
+
Microprocessor
RES
100kΩ
VSS
EN
Motor
controls
EN
R2
GND
Fig. 8
The important parameters of the 22 μF input capacitor are an effective series resistance lower than 3 Ω and a resonant
frequency above 500 kHz.
Copyright © 2006, EM Microelectronic-Marin SA
rev. B / 06.06
8
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
