R
EM6151
Functional Description
VIN Monitoring
Watchdog Timeout Period Description
The power-on reset and the power-down reset are
generated as a response to the external voltage level
applied on the VIN input. The threshold voltage at which
reset is asserted or released (VRESET) is determined by the
external voltage divider between VDD and VSS, as shown on
Fig. 8. A part of VDD is compared to the internal voltage
reference. To determine the values of the divider, the
leakage current at VIN must be taken into account as well as
the current consumption of the divider itself. Low resistor
values will need more current, but high resistor values will
make the reset threshold less accurate at high temperature,
due to a possible leakage current at the VIN input. The sum
of the two resistors (R1 + R2) should stay below 500 kΩ. The
formula is:
The watchdog timeout period is divided into two periods, a
closed window period (TCW) and an open window period
(TOW), see Fig. 4. If no pulse is applied on the TCL input
during the open window period TOW, the RES output goes
low for a time TWDR. When a pulse is applied on the TCL
input, the cycle is restarted with a close window period.
For example if TWD = TPOR = 100ms, TCW = 80 ms, TOW
40ms and TWDR = 2.5ms.
=
When VIN recovers after a drop below VREF, the pad RES is
set low for the time TPOR during which any TCL activation is
disabled.
Timer Clearing and RES Action
VRESET = VREF x (1 + R1/R2).
The watchdog circuit monitors the activity of the processor.
If the user’s software does not send a pulse to the TCL
input within the programmed open window timeout period a
short watchdog RES pulse is generated which is equal to
TWDR (see Fig. 6).
With the open window constraint, new security is added to
conventional watchdogs by monitoring both software cycle
time and execution. Should software clear the watchdog too
quickly (incorrect cycle time) or too slowly (incorrect
execution) it will cause the system to be reset. If software is
stuck in a loop which includes the routine to clear the
watchdog then a conventional watchdog would not make a
system reset even though the software is malfunctioning;
the circuit would make a system reset because the
watchdog would be cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves of
period (TCW + TOW + TWDR). The watchdog will remain in this
state until the next TCL falling edge appears during an open
window, or until a fresh power-up sequence. The system
enable output, EN , can be used to prevent critical control
functions being activated in the event of the system going
into this failure mode (see section “Enable-EN Output”).
The RES output must be pulled up to VDD even if the output
is not used by the system (see Fig 8).
Example: choosing R1 = 200 kΩ and R2 = 100 kΩ gives
VRESET =4.56 V (typical) for version V50 and V53.
At power-up the reset output (RES ) is held low (see Fig. 5).
When VIN becomes greater than VREF, the RES output is
held low for an additional power-on-reset (POR) delay TPOR
(defined with the external resistor connected at ROSC pin).
The TPOR delay prevents repeated toggling of RES even if
VDD voltage drops out and recovers. The TPOR delay allows
the microprocessor’s crystal oscillator time to start and
stabilize and ensures correct recognition of the reset signal
to the microprocessor.
The RES output goes active low generating the power-
down reset whenever VIN falls below VREF. The sensitivity or
reaction time of the internal comparator to the voltage level
on VIN is typically 3 μs.
Timer Programming
The on-chip oscillator allows the user to adjust the power-on
reset (POR) delay TPOR and the watchdog time TWD by
changing the resistor value of the external resistor ROSC
connected between the pin ROSC and VSS (see Fig. 8). The
closed and open window times (TCW and TOW) as well as the
watchdog reset pulse width (TWDR), which are TTCL
dependent, will vary accordingly. The watchdog time TWD
can be obtained with figures 9 to 12 or with the Excel
application EM6151ResCalc.xls available on EM website.
TPOR is equal to TWD with the minimum and maximum
tolerances increased by 1% (For Version 53, TPOR is one
fourth of TWD).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated
by the sequence of events shown in Fig. 6. On power-up,
when the voltage at VIN reaches VREF, the power-on-reset,
POR, delay is initialized and holds RES active for the time
of the POR delay. A TCL pulse will have no effect until this
power-on-reset delay is completed. When the risk exists that
TCL temporarily floats, e.g. during TPOR, a pull-up to VDD is
required on that pin. After the POR delay has elapsed, RES
goes inactive and the watchdog timer starts acting. If no
TCL pulse occurs, RES goes active low for a short time
TWDR after each closed and open window period. A TCL
pulse coming during the open window clears the watchdog
timer. When the TCL pulse occurs too early (during the
closed window), RES goes active and a new timeout
sequence starts. A voltage drop below the VREF level for
longer than typically 3μs overrides the timer and
immediately forces RES active and EN inactive. Any further
TCL pulse has no effect until the next power-up sequence
has completed.
Note that the current consumption increases as the
frequency increases.
CAN-Bus Sleep Mode Detector (version 55)
When the microcontroller goes into a standby mode, it
implies that it does not send any pulses on the TCL input of
the EM6151. After three reset pulse periods (TCW + TOW
+
TWDR) on the RES output, the circuit switches on an internal
resistor of 1 MΩ, and it will have a reset pulse of typically 3
ms every 1 second on the RES output. When a TCL edge
(rising or falling) appears on the TCL input or the power
supply goes down and up, the circuit switches to the ROSC
.
Copyright © 2005, EM Microelectronic-Marin SA
rev. B / 06.06
6
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
