EM6125
1 Absolute Maximum Rating s
Parameter
Supply voltage range
Supply voltage range
Supply voltage range
All input voltages
Voltages at S
0
to S
184
Storage temperature
range
Electrostatic discharge
max. to MIL-STD-883C
method 3015
Maximum soldering
conditions
Symbol
V
DD1,2
V
HV
V
LCD
V
LOGIC
V
DISPLAY
T
STO
V
ESD
T
SMAX
Conditions
-0.3V to +6V
-0.3V to +6V
V
HV
-0.3V to +12V
-0.3V to V
DD1,2
+0.3V
-0.3V to V
LCD
+ 0.3V
-65°C to +150 °C
1000V
250°C
×
10 s
2 Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static
precautions should be taken as for any other CMOS
components. Unless otherwise specified, proper
operation can only occur when all terminal voltages are
kept within the supply voltage range.
3 Operating Conditions
Parameter
Operating
temperature
Logic supply
voltage
High voltage
generator
supply voltage
LCD supply
voltage
Symbol
T
A
V
DD1,2
V
HV
V
LCD
Min.
-40
1.8
2.4 *
3
Typ.
Max.
+85
5.5
5.5
11
°C
V
V
V
2.5
2.5
8
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond
specified electrical characteristics may affect device
reliability or cause malfunction.
* Lower V
HV
voltage is possible until the required V
LCD
voltage is reached.
4 Electrical Characteristics
V
SS1,2
= 0V, V
DD1
= V
DD2
= 1.8V, V
HV
= 2.4V, unless otherwise specified. T
A
= -40°C to +85 °C unless otherwise specified.
Minimum required capacitor: 1µF on V
LCD
, 100nF on V
DD1,2
and V
HV
.
Parameter
Symbol
Test conditions
Min.
Typ.
Max.
Units
Supply Current
Sleep mode
Sleep mode
Normal LCD refresh mode
Normal LCD refresh mode
Partial LCD refresh mode
Control Input Signals
Input leakage
Input capacitance
Low level input voltage
High level input voltage
LCD Outputs
Internally generated LCD
supply voltage
I
DD
I
HV
I
DD
I
HV
I
HV
I
IN
C
IN
V
IL
V
IH
Sleep = 1
Sleep = 1
(note 1)
(note 2)
(note 3)
V
i
= V
ss1
or V
DD1
-1
8
0.3xV
DD1
0.7xV
DD1
V
LCD
00000000b
V
LCD
10001110b
V
LCD
step between 2
consecutive programmed
V
LCD
Level
V bias tolerance
V
LCD
step
V bias tol.
(note 5)
-80
3.02
8.02
35.2
80
10
0.5
15
124
50
nA
21
180
87
1
µA
µA
µA
µA
µA
pF
V
V
V
V
mV
mV
Note 1:
Measured on V
DD1
+ V
DD2
, all outputs open, SDA and SCL at V
SS
, RES at V
DD1
, multiplex rate 81, x5 voltage
multiplier, V
LCD
= 10001110b, DDRAM loaded with checker pattern
Note 2:
Measured on V
HV
, same conditions as (note 1).
Note 3:
Measured on V
HV
, all outputs open, SDA and SCL at V
SS
, RES at V
DD1
, partial display mode,
×
2 voltage multiplier,
V
LCD
= 00101011b, DDRAM loaded with checker pattern.
Note 4:
With internal voltage multiplier, the maximum V
LCD
voltage depends on V
HV
, programmed voltage multiplier and
display load.
Note 5:
V
1
, V
2
, V
3
and V
4
bias levels measured with V
LCD
= 7V, on 1 LCD row driver output and 1 LCD column driver
output, multiplex rate 81, T
A
= 25 °C, load =
±10µA.
Copyright
2001, EM Microelectronic-Marin SA
4
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
