EM4095
Read Only mode with external peak detector
As mentioned above for high Q antennas the voltage on
antenna is high and read sensitivity is limited by
demodulator sensitivity due to capacitive divider. Read
sensitivity (and thus reading range) can be increased by
using external envelope detector circuit. Input is taken on
antenna high voltage side output is directly fed to
CDEC_IN pin. However, the capacitor divider is still
needed for PLL locking. Such configuration is shown in
figure 5, the envelope detector is formed by three
components: D1, R1 and C1.
RDY/CLK
CDC2
1
2
3
4
5
6
16
15
CFCAP
SHD
DEMOD_OUT
14
13
+5V
LA
EM4095
P4095
µP
MOD
12
11
10
9
CRES
CAGND
CDEC
D1
+5V
CDV1
CDV2
7
8
The configuration presented in figure 9 may also be used
for read write applications but it has a drawback in the
case fast recovery of reading is needed after
communication reader to transponder is finished. The
reason is in fact that DC voltage after diode D1 is lost
during modulation and it takes very long time before it is
established again.
C1
R1
Fig. 10
Read/Write mode with external peak detector
Figure 10 presents a solution to that problem. A high
voltage NMOS transistor blocks the discharge path during
modulation, so operating point is preserved. The signal
controlling NMOS gate has to be put low synchronously
with signal MOD, but it can be put high only after the
amplitude on antenna has recovered after modulation.
RDY/CLK
CDC2
1
2
3
4
5
6
16
15
CFCAP
SHD
DEMOD_OUT
14
13
+5V
LA
EM
P
4
4
0
0
9
95
5
µP
MOD
PCB Layout
12
11
10
9
CRES
CAGND
Refer to "EM4095 Application Note" (App. Note 404)
CDEC
D1
+5V
CDV1
CDV2
7
8
C1
R1
Fig. 11
8
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