EM4022
Functional description
Resonance capacitor
The resonance capacitor CR has a nominal value of 110
pF and is trimmed to achieving a high stability over the
whole production. For resonance at 125 kHz an external
14.7 mH coil is required. At 13.65 MHz the required coil
inductance drops to 1.2
µ
H.
Rectifier bridge
Diodes D1-D4 form a full wave rectifier bridge. They
have relatively large forward resistances (100 -200
Ω
).
This is sufficient at 125 kHz, where the output
impedance of the tuned circuit is high, but at 13.5 MHz
the diode resistance becomes significant and external
diodes have to be used to bypass the internal ones. The
diode resistance affects the rate at which the power
capacitor CP can be charged. It also affects the
modulation depth that can be achieved.
Shunt regulator
The shunt regulator has two functions. It limits the
voltage across the logic and in high frequency
applications it limits the voltage across the external
microwave Schottky diodes, which typically have reverse
breakdown voltages of 5 V.
Oscillator
The on-chip RC oscillator has a center frequency of 128
kHz. It gives the main clock of the logic and defines the
effective data/rate.
Power-on reset (PON)
The reset signal keeps the logic in reset when the supply
voltage is lower than the threshold voltage.
This
prevents incorrect operation and spurious transmissions
when the supply voltage is too low for the oscillator and
logic to work properly. It also ensures that transistor Q2
is off and transistor Q1 is on during power-up to ensure
that the chip starts up.
Modulation transistor
The N channel transistor Q2 is used to modulate the
transponder coil or antenna. When it is turned on it loads
the antenna or coil, thereby changing the load seen by
the reader antenna or coil, and effectively changing the
amount of energy that is reflected to the reader. Its low
on resistance is especially designed for high frequency
applications.
Charge preservation transistor
The P channel transistor Q1 is turned off whenever the
modulation transistor Q2 is turned on to prevent Q2 from
discharging the power storage capacitor. This is done in
a non-overlapping manner, i.e. Q1 is first turned off
before Q2 is turned on, and Q2 is turned off before Q1 is
turned on.
Gap detection
Poly-silicon diode DG is used to detect a gap in the
illuminating field. It is a minimum sized diode with
forward resistance in the order of 2 k
Ω.==
The low pass
filter shown diagrammatically as CG and RG actually
consists of a pull-up transistor (approximately 100 k
Ω)
in
conjunction with the parasitic capacitance of the GAP
input pad (approximately 2.5 pF).
Through the diode the GAP input will be pulled low
during each negative going cycle of the carrier. When
the carrier is switched off, the GAP input will be pulled
high by the pull-up transistor.
At very high carrier frequencies (> 100 MHz) the carrier
will be filtered out, so that the GAP input will be low
continuously when the carrier is present. When the
carrier disappears, the GAP input will go high with the
time constant of the low pass filter. At very low
frequencies the GAP input will go high and low at each
cycle of the carrier, and will stay high when the carrier
disappears. To detect the gap, the logic must check for
a high period longer than the maximum high period of
the carrier.
As the rise and fall times of the GAP can be slow, a
Schmitt trigger is used to buffer the GAP input.
LOGIC block
Depending on the state of the SI input at power-up, the
EM4022 either enters a test mode (SI = 1) or its normal
operating mode (SI = 0). The SI pin is internally pulled
down, so that it can be left open for normal operation.
After the power-on reset has disappeared, the chip boots
by reading the SEED and CTL ROMs.
The chip then enters its normal operating mode, which
basically consists of clocking a 16 bit timer counter with
the bit rate clock until it compares with the number in the
random number generator. At this point a code (which is
stored in the ID ROM) is transmitted with the correct
preamble at the correct data rate and encoded correctly.
The random number generator is clocked to generate a
new pseudo random number, and the 16 bit counter is
reset to start a new delay.
The width of the comparison between the 16 bit random
number and the 16 bit delay count determines the
maximum possible delay between transmissions
(repetition rate). Any one of eight maximum delay
settings can be pre-programmed.
The basic free-running mode as described above can be
modified by the reception of GAP (MUTE and ACK)
signals, if these are enabled by the CTL bits.
If an ACK signal is received after transmission of a code,
the chip either turns itself off completely or reduces the
rate at which the delay counter is clocked, thereby
slowing down the rate at which codes are transmitted.
If a MUTE signal is received while the chip is not
transmitting, the current operation of the chip is
interrupted for 128 clock periods, after which it continues
normally. Reception of more MUTEs during the sleep
state restarts the sleep state. The sleep state is also
terminated by the reception of a WAKE-UP signal (an
ACK signal to a chip which has just completed
transmitting).
Copyright
2002, EM Microelectronic-Marin SA
5
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
