EM78P5840/5841/5842
8-bit Micro-controller
VII.3 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
CONT (Control Register)
7
6
5
4
3
2
1
0
P70EG
R/W-1
INT
TS
RETBK
R/W-1
PAB
R/W-1
PSR2
R/W-1
PSR1
R/W-1
PSR0
R/W-1
R/W-0
R/W-1
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC rate
1:2
WDT rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:4
1:16
1:32
1:64
1:128
1:256
1:8
1:16
1:32
1:64
1:128
Bit 3(PAB) : Prescaler assignment bit
0/1 Î TCC/WDT
Bit 4(RETBK) : Return value backup control for interrupt routine
0/1 Î disable/enable
When this bit is set to 1, the CPU will store ACC,R3 status and R5 PAGE automatically after an interrupt is
triggered. And it will be restored after instruction RETI. When this bit is set to 0, the user need to store ACC,
R3 and R5 PAGE in user program.
Bit 5(TS) : TCC signal source
0 Î Internal instruction cycle clock
1 Î IRC output
Bit 6 (INT) : INT enable flag
0 Î interrupt masked by DISI or hardware interrupt
1 Î interrupt enabled by ENI/RETI instructions
Bit 7 (P70EG): If switch port70 to INT0 input, P70EG can select the interrupt toggle type.
0 Î P70 's interruption source is a rising edge signal and falling edge signal.
1 Î P70 's interruption source is a falling edge signal.
CONT register is readable (CONTR) and writable (CONTW).
TCC and WDT :
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC
only or WDT only at the same time.
An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT
register.
See the prescaler ratio in CONT register.
Fig.5 depicts the circuit diagram of TCC/WDT.
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* This specification is subject to change without notice.
17
2004/11/10 V2.6
ELAN [ ELAN MICROELECTRONICS CORP ]
