欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM78P5840 参数 Datasheet PDF下载

EM78P5840图片预览
型号: EM78P5840
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8 BIT MICROCONTROLLER]
分类和应用: 微控制器
文件页数/大小: 48 页 / 467 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
 浏览型号EM78P5840的Datasheet PDF文件第7页浏览型号EM78P5840的Datasheet PDF文件第8页浏览型号EM78P5840的Datasheet PDF文件第9页浏览型号EM78P5840的Datasheet PDF文件第10页浏览型号EM78P5840的Datasheet PDF文件第12页浏览型号EM78P5840的Datasheet PDF文件第13页浏览型号EM78P5840的Datasheet PDF文件第14页浏览型号EM78P5840的Datasheet PDF文件第15页  
EM78P5840/5841/5842  
8-bit Micro-controller  
"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are  
cleared to "0''.  
"TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change.  
The most significant bit (A10~A11) will be loaded with the contents of bit PS0~PS1 in the status register (R5  
PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.  
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC,  
R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.  
R5(PAGE)  
CALL  
and  
INTERRUPT  
STACK1  
STACK2  
STACK3  
STACK4  
STACK5  
STACK6  
STACK7  
STACK8  
A11 A10  
A9 A8  
A7~A0  
store  
RET  
RETL  
RETI  
0 0  
0 1  
PAGE0 00000~003FF  
PAGE1 00400~007FF  
ACC,R3,R5(PAGE)  
restore  
1 0  
1 1  
PAGE2 00800~00BFF  
PAGE3 00C00~00FFF  
Fig.3 Program counter organization  
R3 (Status, Page selection)  
(Status flag, Page selection bits)  
7
6
5
4
T
R
3
P
R
2
Z
1
0
C
RPAGE1 RPAGE0 IOCPAGE  
R/W-0 R/W-0 R/W-0  
Bit 0(C) : Carry flag  
DC  
R/W  
R/W  
R/W  
Bit 1(DC) : Auxiliary carry flag  
Bit 2(Z) : Zero flag  
Bit 3(P) : Power down bit  
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.  
Bit 4(T) : Time-out bit  
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.  
EVENT  
T
P
REMARK  
WDT wake up from sleep mode  
WDT time out (not sleep mode)  
/RESET wake up from sleep  
Power up  
0
0
1
1
x
0
1
0
1
Low pulse on /RESET  
X
x : don't care  
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page  
Please refer to Fig.4 control register configuration for details.  
0/1 Î IOC page0 / IOC page1  
Bit 6(RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page  
Please refer to VII.1 Operational registers for detail register configuration.  
__________________________________________________________________________________________________________________________________________________________________  
* This specification is subject to change without notice.  
9
2004/11/10 V2.6  
 复制成功!