EM78P5840N/41N/42N
8-Bit Microcontrollers
The following table lists the wake-up sources and the resulting status after wake-up:
Wake-up Signal
Sleep Mode
RA (7, 6)=(0, 0)
+ SLEP
-
TCC Time-out
IOCF Bit 0=1
No function
No function
Counter 1 Time out
IOCF Bit 1=1
WDT Time out
Reset and Jump to Address 0
Reset and Jump to Address 0
Port 7 (0, 1, 3)*
* Port 70 wake-up function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger
(controlled by CONT register Bit7).
Port 71 wake-up function is controlled by IOCF Bit 4. It is a falling edge trigger.
Port 73 wake-up function is controlled by IOCF bit 7. It is a falling edge trigger.
7.9 Interrupt
RF is the interrupt status register that records the interrupt request in a flag bit. IOCF is
the interrupt mask register. Global interrupt is enabled by the ENI instruction and is
disabled by the DISI instruction. When one of the interrupts (when enabled) is
generated, it will prompt the next instruction to be fetched from Address 008H. Once in
the interrupt service routine, the source of the interrupt can be determined by polling
the flag bits in the RF register. The interrupt flag bit must be cleared through software
before leaving the interrupt service routine and enabling interrupts to avoid recursive
interrupts.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
