EM78P510N
8-Bit Microcontrollers
Note: Open-drain is not shown in the figure.
Figure 6-5 Circuits of I/O Port and I/O Control Register for Ports 7~ 9, and Ports A ~ C
6.5 Reset and Wake-up
A Reset can be caused by:
Power-on reset
WDT timeout (if enabled)
LVR Reset
RESET pin pulls low
NOTE
The power-on reset circuit is always enabled, it will reset the CPU at 2.3V and power
consumption is 0.5µA.
Once a Reset occurs, the following functions are performed:
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The TCC/Watchdog timer and prescaler are cleared.
When power is on, all bits of R5 and R6 are cleared.
The other registers are described in Table 2
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Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
