EM78P510N
8-Bit Microcontrollers
6.2.39 Bank 3 R6 URS (UART Status)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD8
EVEN
PRE
PRERR
OVERR
FMERR
URBF
RXE
Bit 7 (URRD8): Receiving Data Bit 8
Bit 6 (EVEN): Select Parity Check
0 : Odd parity
1 : Even parity
Bit 5 (PRE):
Enable Parity Addition
0 : Disable
1 : Enable
Bit 4 (PRERR): Parity Error Flag
Set to 1 when parity error occurs and cleared to 0 by software.
Bit 3 (OVERR): Over Running Error Flag
Set to 1 when overrun error occurs and cleared to 0 by software.
Bit 2 (FMERR): Framing Error Flag
Set to 1 when framing error occurs and cleared to 0 by software.
Bit 1 (URBF): UART Read Buffer Full Flag
Set to 1 when one character is received. Reset to 0 automatically
when read from URS register. URBF will be cleared by hardware
when enabling receiving. And URBF bit is read-only. Therefore,
reading the URS register is necessary to avoid overrun error.
Bit 0 (RXE):
Enable Receiving
0 : Disable
1 : Enable
6.2.40 Bank 3 R7 URRD (UART_RD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD7
URRD6
URRD5
URRD4
URRD3
URRD2
URRD1
URRD0
Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only.
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Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
