EM78P510N
8-Bit Microcontrollers
6.8 Interrupt
Registers for Interrupt
R_BANK Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T1IE LVDIE ADIE SPIE URTIE EXIE9 EXIE8 TCIE
Bank 0
Bank 0
Bank 1
Bank 1
Bank 2
0x0E
0x0F
0X0E
0X0F
0X09
IMR
ISR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T1IF LVDIF ADIF SPIF URTIF EXIF9 EXIF8 TCIF
R/W
EXIE7 EXIE6 EXIE5 EXIE4 EXIE3 EXIE2 EXIE1 EXIE0
R/W R/W R/W R/W R/W R/W R/W R/W
EXIF7 EXIF6 EXIF5 EXIF4 EXIF3 EXIF2 EXIF1 EXIF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EIMR
EISR
T2CR
R/W
T2IF
R/W
R/W
T2IE
R/W
R/W
T2EN T2MS1 T2MS0 T2P2
R/W R/W R/W R/W
R/W
R/W
R/W
R/W
T2P1
R/W
R/W
T2P0
R/W
The EM78P510N has ten interrupt sources as listed below:
TCC overflow interrupt
External interrupt pin
Watch timer interrupt
Timer 1 overflow interrupt
Timer 2 overflow interrupt
A/D conversion complete interrupt
UART transmit interrupt
SPI transmit/receive interrupt
Low voltage detector
This IC has internal interrupts which are falling edge triggered, as follows: TCC timer
overflow interrupt, and two 8-bit upper counter/timer overflow interrupt. If these
interrupt sources change signal from high to low, the RF register will generate a “1” flag
to the corresponding register if RE register is enabled.
RF is the interrupt status register which records the interrupt request in flag bit. RE is
the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (when enabled) is generated,
it will cause the next instruction to be fetched from address 0003H~001BH according to
the interrupt source.
For EM78P510N, each individual interrupt source has its own interrupt vector as
depicted in Table 7.
Before the interrupt subroutine is executed, the contents of ACC, R3[4:0], R5 and the
R6 register will be saved by hardware. After the interrupt service routine is finished,
ACC, R3[4:0], R5 and R6 will be pushed back. While in interrupt service routine, other
interrupt service routine should not be allowed to be executed, so if other interrupts
occur in an interrupt service routine, the hardware will save this interrupt, after which
when interrupt service routine is completed, the next interrupt service routine will be
executed.
58 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
