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EM78P510NAM 参数 Datasheet PDF下载

EM78P510NAM图片预览
型号: EM78P510NAM
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微 [8-Bit Microprocessor with OTP ROM]
分类和应用: OTP只读存储器
文件页数/大小: 116 页 / 2156 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P510N  
8-Bit Microcontrollers  
6.3 TCC/WDT Pre-scaler  
Registers for the TCC/WDT Circuit  
R_BANK Address NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0  
Bank 0  
Bank 0  
Bank 0  
0X0D  
0x0E  
0x0F  
TWTCR WDTE WPSR2 WPSR1 WPSR0 TCCS TPSR2 TPSR1 TPSR0  
R/W R/W R/W R/W R/W R/W R/W R/W  
IMR  
T1IE LVDIE ADIE SPIE URTIE EXIE9 EXIE8 TCIE  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
ISR  
T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
There are two 8-bit counters available as prescalers for the TCC and WDT, respectively.  
The TPSR0~TPSR2 bits of the Bank 0 RD (TWTCR) register are used to determine the  
ratio of the TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the Bank 0 RD  
(TWTCR) register are used to determine the WDT prescaler. The prescaler  
(TPSR0~TPSR2) will be cleared by the instructions each time they are written into TCC.  
The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Fig.6-4  
depicts the circuit diagram of TCC/WDT.  
R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal clock main  
clock or sub clock (32.768kHz). If TCC signal source is from the internal clock, TCC will  
be incremented by 1 at every instruction cycle (without prescaler). As illustrated in Fig.  
6-4. The watchdog timer is a free running on-chip RC oscillator. The WDT will continue  
running even after the oscillator driver has been turned off (i.e. in sleep mode). During  
normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to  
reset. The WDT can be enabled or disabled at any time during the normal mode by  
software programming. Refer to WDTE bit of Bank 0 RD (TWTCR) register. With no  
prescaler, the WDT time-out period is approximately 18 ms1.  
1 Note: VDD=5V, Setup time period = 16.5ms ± 30% VDD=3V, Setup time period = 18ms ± 30%  
40 •  
Product Specification (V0.9) 09.12.2006  
(This specification is subject to change without further notice)  
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