欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM78P510N 参数 Datasheet PDF下载

EM78P510N图片预览
型号: EM78P510N
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微 [8-Bit Microprocessor with OTP ROM]
分类和应用: 局域网OTP只读存储器
文件页数/大小: 116 页 / 2156 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
 浏览型号EM78P510N的Datasheet PDF文件第76页浏览型号EM78P510N的Datasheet PDF文件第77页浏览型号EM78P510N的Datasheet PDF文件第78页浏览型号EM78P510N的Datasheet PDF文件第79页浏览型号EM78P510N的Datasheet PDF文件第81页浏览型号EM78P510N的Datasheet PDF文件第82页浏览型号EM78P510N的Datasheet PDF文件第83页浏览型号EM78P510N的Datasheet PDF文件第84页  
EM78P510N  
8-Bit Microcontrollers  
6.11.2 Transmitting  
In transmitting serial data, the UART operates as follows:  
1. Set the TXE bit of the URC register to enable the UART transmission function.  
2. Write data into the URTD register and the UTBE bit of the URC register will be set  
by hardware.  
3. Then start transmitting.  
4. Serially transmitted data are transmitted in the following order from the TX pin.  
5. Start bit: one “0” bit is output.  
6. Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.  
7. Parity bit: one parity bit (odd or even selectable) is output.  
8. Stop bit: one “1” bit (stop bit) is output.  
Mark state: output “1” continues until the start bit of the next transmitted data.  
After transmitting the stop bit, the UART generates a TBEF interrupt (if enabled).  
6.11.3 Receiving  
In receiving, the UART operates as follows:  
1. Set RXE bit of the URS register to enable the UART receiving function. The UART  
monitors the RX pin and synchronizes internally when it detects a start bit.  
2. Receive data is shifted into the URRD register in the order from LSB to MSB.  
3. The parity bit and the stop bit are received. After one character is received, the  
URBF bit of the URS register will be set to 1. This means UART interrupt will occur.  
4. The UART makes the following checks:  
(a) Parity check: The number of 1 of the received data must match the even or odd  
parity setting of the EVEN bit in the URS register.  
(b) Frame check: The start bit must be 0 and the stop bit must be 1.  
(c) Overrun check: The URBF bit of the URS register must be cleared (that means  
the URRD register should be read out) before the next received data is loaded  
into the URRD register.  
If any checks failed, the URTIF interrupt will be generated (if enabled), and an error  
flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be  
cleared by software otherwise, URTIF interrupt will occur when the next byte is  
received.  
5. Read received data from URRD register. And URBF bit will be cleared by  
hardware.  
74 •  
Product Specification (V0.9) 09.12.2006  
(This specification is subject to change without further notice)  
 复制成功!