EM78P458/459
OTP ROM
affected by the operation. The symbol "k" represents an 8 or 10-bit constant or literal value.
Table 16 The list of the instruction set of EM78P458/459
INSTRUCTION BINARY HEX MNEMONIC
OPERATION
STATUS AFFECTED
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
0014
001r
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
NOP
No Operation
Decimal Adjust A
A → CONT
None
DAA
C
CONTW
SLEP
None
T,P
0 → WDT, Stop oscillator
0 → WDT
WDTC
T,P
IOW R
None <Note1>
A → IOCR
ENI
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC, Enable Interrupt
CONT → A
None
DISI
None
RET
None
RETI
None
CONTR
IOR R
None
None <Note1>
IOCR → A
MOV R,A
CLRA
None
A → R
Z
Z
0 → A
CLR R
0 → R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
Z,C,DC
R-A → A
Z,C,DC
R-A → R
Z
R-1 → A
Z
R-1 → R
Z
A ∨ VR → A
Z
A ∨ VR → R
Z
A & R → A
Z
A & R → R
Z
A ⊕ R → A
Z
A ⊕ R → R
Z,C,DC
A + R → A
Z,C,DC
A + R → R
Z
R → A
Z
Z
R → R
/R → A
Z
/R → R
Z
R+1 → A
Z
R+1 → R
DJZA R
DJZ R
None
None
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA R
C
RRC R
C
RLCA R
RLC R
C
C
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
07rr
07rr
07rr
0xxx
SWAP R
JZA R
JZ R
None
None
None
BC R,b
None <Note2>
This specification is subject to change without prior notice.
52
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
