EM78P350N
8-Bit Microprocessor with OTP ROM
6.10.4 PWM Duty Cycle(DTX: DT1H/ DT1L, DT2H/ DT2L and
DT3H/DT3L; DLX: DL1H/DL1L, DL2H/DL2L
and DL3H/DL3L )
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX
to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared.
DTX can be loaded anytime. However, it cannot be latched into DLX until the current
value of DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
Duty Cycle = (DTX) * (1/Fosc) * CLKS/2 * (TMRX prescale value )
Example:
DTX=10; Fosc=4MHz; CLKS bit of Code Option Register = 0 (2 oscillator
periods); TMRX (0,0,0)=1:2, then Duty Cycle = 10 * (1/4M) * 2/2 * 2 =5us
6.10.5 Comparator X
Changing the output status while a match occurs will simultaneously set the TMRXIF
flag.
6.10.6 PWM Programming Process/Steps
1. Load PRDX with the PWM time period.
2. Load DTX with the PWM Duty Cycle.
3. Enable interrupt function by writing IOCF, if required.
4. Set PWMX pin to be output by writing a desired value to Bank1 R5 or R6.
5. Load a desired value to Bank1 R5 or R6 with TMRX prescaler value and enable
both PWMX and TMRX.
6.11 Timer
6.11.1 Overview
Timer 1 (TMR1), Timer 2 (TMR2), and Timer 3 (TMR3) (TMRX) are 10-bit clock counters
with programmable prescalers. They are designed for the PWM module as baud rate
clock generators. TMRX can be read only. The Timer 1, Timer 2, and Timer 3 will stop
running when sleep mode occurs with AD conversion not running. However, if AD
conversion is running when sleep mode occurs, the Timer 1, Timer 2 and Timer 3, will
keep on running.
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Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
