EM78P350N
8-Bit Microprocessor with OTP ROM
6 Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a pointer, actually accesses the
data pointed by the RAM Select Register (R4).
6.1.2 R1 (Time Clock/Counter)
Incremented by an external signal edge through the TCC pin, or by the instruction
cycle clock.
External signal of TCC trigger pulse width must be greater than one instruction.
The signals to increment the counter are determined by Bit 4 and Bit 5 of the CONT
register.
Writable and readable as any other registers.
6.1.3 R2 (Program Counter) and Stack
000H
008H
Reset Vector
Interrupt Vector
PC (A12 ~ A0)
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 8
1FFFH
Fig. 6-1 Program Counter Organization
R2 and hardware stacks are 12-bit wide. The structure is depicted in the table
under Section 6.1.3.1 Data Memory Configuration (next section).
Generates 8K×13 bits on-chip ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a RESET condition occurs.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to jump to any location within a page.
6 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
