EM78P312N
8-Bit Microcontroller
VDD
D
CLK
Q
CLK
Oscillator
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT Timeout
Setup Time
RESET
WDT
/RESET
Fig. 5-28 Controller Reset Block Diagram
5.15 Interrupt
The EM78P312N has 15 interrupts (9 external, 6 internal) as listed below:
Table 9 Interrupt Vector
Interrupt Source
Enable Condition Int. Flag Int. Vector Priority
Internal /
Reset
−
−
0000
High 0
External
Internal
External
Internal
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
External
Internal
Internal
External
WDT
ENI + WDTEN
ENI + INT0EN=1
ENI + TCIE0=1
ENI + EXIE1=1
ENI + TBIE=1
ENI + UTIE=1
ENI + URIE=1
ENI+UERRIE=1
ENI + TCIE3=1
ENI + SPIE=1
ENI + TCIE4=1
ENI + EXIE3=1
ENI + ADIE=1
ENI + TCIE2=1
ENI + EXIE5=1
WDTIF
EXIEF0
TCIF0
EXIF1
TBIF
0003
0006
0009
000F
0012
0015
0018
001B
0021
0024
0027
002A
0030
0033
0036
1
INT0
2
TCC
3
INT1
4
TBT
5
UART Transmit
TBEF
TBFF
6
7
UART Receive
UART Receive error
UERRIF
TCIF3
SPIF
8
TC3
SPI
9
10
TC4
INT3
AD
TCIF4
EXIF3
ADIF
11
12
13
TC2
INT5
TCIF2
EXIF5
14
Low 15
ISFR0, ISFR1 and ISFR2 are the interrupt status registers that record the interrupt
requests in the relative flags/bits. IMR1 and IMR2 are the interrupt mask registers. The
global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
When one of the interrupts (enabled) occurs, the next instruction will be fetched from
individual address. The interrupt flag bit must be cleared by instructions before leaving
the interrupt service routine and before interrupts are enabled to avoid recursive
interrupts.
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
• 49
ELAN [ ELAN MICROELECTRONICS CORP ]
