EM78P312N
8-Bit Microcontroller
5.7 UART (Universal Asynchronous Receiver/Transmitter)
Registers for UART Circuit
R_BANK Address Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXE
R/W
0
URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 0
SFR
0X05
0X06
0X07
0X08
0X09
0x0F
0x0F
URC1
URC2
URS
R/W
0
R/W
0
R/W
SBIM1
R/W
R/W
SBIM0 UINVEN
R/W R/W
R/W
R/W
0
R
0
--
--
--
--
--
URRD8 EVEN
R/W R/W
PRE
PRERR OVERR FMERR URBF
R/W R/W R/W
RXE
R/W
R/W
R
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
URRD
URTD
ISFR2
IMR2
R
R
R
R
R
R
R
R
URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0
W
0
W
W
W
W
W
W
0
W
UERRIF RBFF
TBEF
R/W
UTIE
R/W
TBIF
R/W
TBIE
R/W
EXIF1
R/W
TCIF0
R/W
--
0
R/W
UERRIE
R/W
R/W
URIE
R/W
--
0
EXIE1
R/W
TCIE0
R/W
--
--
TC4
Baud rate
generator
Fsystem
RX Control
Interrupt
Control
TX Control
TXE
RXE
RX
RX shift register
Parity control
TX
URRD
URTD8
URRD8
Error flag
Data Bus
URTD
UINVEN
UINVEN
Fig. 5-10 Function Block Diagram
In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received
character is individually synchronized by framing it with a start bit and stop bit.
Full duplex data transfer is possible since the UART has independent transmit and
receive sections. Double buffering for both sections allows the UART to be
programmed for continuous data transfer.
28 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)