EM78P312N
8-Bit Microcontroller
5.4 CPU Operation Mode
Registers for CPU Operation Mode
R_BANK Address
NAME
SCR
−
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
0X05
0
PS2
R/W
PS1
R/W
PS0
R/W
0
1
SIS
REM
−
−
−
−
−
R/W
R/W
* R_BANK: Register Bank (Bits 7, 6 of R3), R/W: Read/Write
Reset Occurs
SIS=0 + SLEP
SIS=1 + SLEP
Idle Mode
CPU : Halts
Fosc: Oscillates
Normal Mode
CPU : Operating
Fosc: Oscillates
Sleep Mode
CPU : Halts
Fosc: Stops
Interrupt
/SLEEP Pin Input
Fig. 5-4 Operation Mode and Switching
Table 2. Mode Switching Control
Mode Switch
Switch Method
Note
Normal Æ Sleep
Sleep Æ Normal
Normal Æ Idle
Idle Æ Normal
Set SIS = 1, execute SLEP instruction
/SLEEP pin wake up
−
−
−
−
Set SIS = 0, execute SLEP instruction
Interrupt
Table 3. Operation Mode
Operation Mode
Reset
On-chip
Peripherals
Frequency
CPU Code
Reset
Fosc
Reset
Fosc
Halt
Turn on
Turn off
Normal
Idle
Signal
Clock
Halt
Sleep
In Normal mode, the CPU core and on-chip peripherals operate in oscillator frequency.
In Idle mode, the CPU core halts, but the on-chip peripheral and oscillator circuit remain
active. Idle mode is released to Normal mode by any interrupt source. If the ENI
instruction is set, an interrupt will be serviced first followed by executing the next
instruction which is after the Idle mode is released and the interrupt service is finished.
If the ENI instruction is not set, the next instruction will be executed which is after the
Idle mode start instruction. Idle mode can also be released by setting the /RESET pin
to low and executing a reset operation.
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
