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EM78P259N 参数 Datasheet PDF下载

EM78P259N图片预览
型号: EM78P259N
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微 [8-Bit Microprocessor with OTP ROM]
分类和应用: OTP只读存储器
文件页数/大小: 88 页 / 2435 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P259N/260N  
8-Bit Microprocessor with OTP ROM  
6.10.3 Using a Comparator as an Operation Amplifier  
The comparator can be used as an operation amplifier if a feedback resistor is  
externally connected from the input to the output. In this case, the Schmitt trigger can  
be disabled for power saving purposes, by setting Bit 4, Bit 3<COS1, COS0> of the  
IOC80 register to <1,1>. See table under Section 6.2.4, IOC80 (Comparator and TCCA  
Control Registers) for Comparator/OP select bits function description.  
NOTE  
Under Operation Amplifier:  
The CMPIE (IOCE0.4), CMPWE (RE.2), and CMPIF (RE.4) bits are invalid.  
The comparator interrupt is invalid.  
The comparator wake-up is invalid.  
6.10.4 Comparator Interrupt  
CMPIE (IOCE0.4) must be enabled for the “ENI” instruction to take effect  
Interrupt is triggered whenever a change occurs on the comparator output pin  
The actual change on the pin can be determined by reading the Bit CMPOUT,  
IOC80<5>.  
CMPIF (RE.4), the comparator interrupt flag, can only be cleared by software  
6.10.5 Wake-up from SLEEP Mode  
If the CMPWE bit of the RE register is set to “1,” the comparator remains active and  
the interrupt remains functional, even under SLEEP mode.  
If a mismatch occurs, the change will wake up the device from SLEEP mode.  
The power consumption should be taken into consideration for the benefit of energy  
conservation.  
If the function is unemployed during SLEEP mode, turn off the comparator before  
entering into sleep mode.  
The Comparator is considered completed as determined by:  
1. COS1 and COS0 bits of IOC80 register setting selects Comparator.  
2. CMPIF bit of RE register is set to “1”.  
3. CMPWE bit of RE register is set to “1”. Wakes-up from Comparator (where it  
remains in operation during sleep mode)  
4. Wakes-up and executes the next instruction, if CMPIE bit of IOCE0 is enabled and  
the “DISI” instruction is executed.  
5. Wake-up and enters into Interrupt vector (address 0x00F), if ADIE bit of IOCE0 is  
enabled and the “ENI” instruction is executed  
6. Enters into Interrupt vector (address 0x00F), if CMPIE bit of IOCE0 is enabled and  
the “ENI” instruction is executed.  
60 •  
Product Specification (V1.0) 06.16.2005  
(This specification is subject to change without further notice)  
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