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EM78P259NSO14J 参数 Datasheet PDF下载

EM78P259NSO14J图片预览
型号: EM78P259NSO14J
PDF下载: 下载PDF文件 查看货源
内容描述: [EM78Q153SN EM78P153SP EM78P153SN EM78156EH EM78156EP EM78156EM EM78156EKM EM78Q156ELP EM78Q156ELM EM78Q156ELKM EM78P156ELP EM78P156ELM EM78P156ELKM EM78P156NP EM78P156NM EM78447SH EM78447SAP EM78447SAM EM78447SAS EM78447SBP EM78447SBWM EM78Q447SH EM78Q447SAP EM78Q447SAM EM78Q447SBP EM78Q447SBWM EM78P447SAP EM78P447SAM EM78P447SAS EM78P447SBP EM78P447SBWM EM78Q257 EM78Q257AP EM78Q257AM EM78Q257BP EM78Q257BM EM78P257AP EM78P257AM EM78P257BP EM78P257BM EM78451H EM78451P EM78451AQ EM]
分类和应用:
文件页数/大小: 81 页 / 2574 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P258N  
8-Bit Microprocessor with OTP ROM  
External interrupt equipped with digital noise rejection circuit (input pulse less than 8  
system clocks time) is eliminated as noise. However, under Low XTAL oscillator (LXT)  
mode the noise rejection circuit will be disabled. Edge selection is possible with INTE  
of CONT. When an interrupt is generated by the External interrupt (when enabled), the  
next instruction will be fetched from address 003H. Refer to the Word 1 Bits 9 & 8  
(Section 6.14.2, Code Option Register (Word1)) for digital noise rejection definition  
RF and RE are the interrupt status register that records the interrupt requests in the  
relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt  
is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the  
interrupt service routine, the source of an interrupt can be determined by polling the flag  
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the  
interrupt service routine to avoid recursive interrupts.  
The flag (except for the ICIF bit) in the Interrupt Status Register (RF) is set regardless of  
the ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0  
(refer to figure below). The RETI instruction ends the interrupt routine and enables the  
global interrupt (the ENI execution).  
When an interrupt is generated by the Timer clock/counter (if enabled), the next  
instruction will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB,  
and TCCC respectively).  
When an interrupt is generated by the AD conversion is completed (if enabled), the  
next instruction will be fetched from Address 00CH.  
When an interrupt is generated by the High time / Low time down counter underflow  
(when enabled), the next instruction will be fetched from Address 012 and 015H (High  
time and Low time respectively).  
Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4  
registers will be saved by the hardware. If another interrupt occurs, the ACC, R3, and  
R4 will be replaced by the new interrupt. After the interrupt service routine is completed,  
the ACC, R3, and R4 registers are restored.  
40 •  
Product Specification (V1.0) 06.16.2005  
(This specification is subject to change without further notice)  
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